An important characteristic of power transistors is the turn-on resistance R.sub.DS(on) that can be achieved on a given area R.sub.Si. In the optimization of a component with respect to component area and thus to cost, the specific turn-on resistance R.sub.DS(on) * R.sub.Si must be minimized with a given overall resistance of the component. The specific turn-on resistance can be reduced by making the area of the MOS cells smaller in the voltage range below 50 V which, in particular, is of significance in the field of automotive technology.
For reducing the area requirement of the MOS cell, it is known to vertically construct a MOS transistor (see, for example, D. Ueda et al., IEEE Vol. ED-34, 1987, pages 926-930; H.-R. Chang et al., IEEE Vol. ED-36, 1989, pages 1824-1829; K. Shenai, IEEE Ed Lett. Vol. 12, 1991, pages 108-110). The resulting reduction of the space requirement is dependent on the maximum degree of structural fineness that can be achieved in the manufacturing method.
In vertical MOS transistors, source regions that, for example, are n-doped and well regions that, for example, are p-doped are connected to one another with an ohmic contact at the surface of a silicon substrate. The ohmic contact is realized via a metallization at the surface. The gate electrode is arranged in a trench in the vertical MOS transistor and this trench proceeds perpendicularly relative to the surface of the substrate. The drain region is located under source region and the well in the substrate.
D. Ueda et al., IEEE Vol. ED-34, 1987, pages 926-930 discloses that a silicon wafer that, for example, is n.sup.+ -doped and at whose surface is a small n.sup.- -doped epitaxial layer can be employed in a method for manufacturing a power MOSFET. By implantation via a mask, a p-doped layer that forms the well is formed in the surface of this substrate. Stripe-shaped source regions that are n.sup.+ -doped and that proceed parallel to one another are produced in the surface by implantation using a further mask. A part of the p-doped well at the surface of the substrate extends between respectively two neighboring, stripe-shaped source regions. Using a nitride mask, rectangular trenches that extend down into the n.sup.- -doped epitaxial layer are produced perpendicularly relative to the course of the stripe-shaped source regions. The trenches are likewise arranged in the form of parallel stripes that form a right angle with the stripes of the source regions. The trenches are filled with polysilicon after the production of a gate dielectric. The polysilicon is etched back, whereby the contact area for the MOS gate contact must be covered with a fourth mask. Polysilicon in the upper region of the trenches is converted into SiO.sub.2 by local oxidation. An aluminum metallization is applied after removal of a Si.sub.3 N.sub.4 mask employed for trench etching and for local oxidation and after opening of the contact hole (via hole) to the MOS gate contact area, this aluminum metallization contacting the source regions and the p-doped well regions.
The parts of the p-doped well extending up to the surface of the substrate must have an expanse that at least corresponds to the minimum contact area. This is also valid for the n-doped source regions. Thus, this involves a minimum space requirement at the wafer surface.
Over and above this, parasitic bipolar effects can arise because of the large spacings in the alternating n.sup.+ -doped source regions and p-doped well regions at the surface of the substrate.